Analog-to-digital converters (ADC's) translate an analog signal into a digital representation of that signal. One type that can be manufactured using relatively inexpensive integrated circuit (IC) techniques is the charge redistribution (or charge balance) ADC. Generally, this sort of converter operates by first trapping a quantity of charge related to a voltage to be measured in a sampling capacitor, and then determining the amount of trapped charge using a capacitive ladder circuit. The ladder circuit typically includes a series of binary-weighted capacitors that each have a common plate connected to the sampling capacitor, with each capacitor in the ladder corresponding to a single bit of the converter. The smallest ladder capacitor corresponds to the least significant bit (LSB) of the converter, and the remaining capacitors are each twice as large as the last, with the largest one corresponding to the most significant bit (MSB) of the converter.
To determine the amount of charge trapped in the sampling capacitor, and hence the value of the voltage to be measured, charge redistribution converters usually switch the ladder capacitors one at a time between ground and a precise voltage reference. Each time the converter switches a ladder capacitor, the sampling capacitor and the ladder form different capacitive voltage divider between ground and the reference voltage, and the converter tests the output of that divider with a comparator. Depending on the result of the test, the converter leaves the tested capacitor connected either to the reference or to ground, and sets its corresponding bit to either a one or a zero. Once the converter has tested every ladder capacitor, it can provide the weighted sum of all of the corresponding bits on a digital output as a measure of the voltage.
Average l/f noise levels generally impose a lower limit on the size of the MSB capacitor in a binary-weighted ladder in an ADC IC. Testing each of the most significant bits therefore typically involves large charge transfers from the reference, which can disturb the converter's reference voltage for a significant amount of time. Allowing the reference to stabilize between these tests can constrain the maximum speed of the ADC.
One approach to increasing the speed of charge redistribution converters is to successively approximate a certain number of a single converter's most significant bits at less than a desired accuracy, by decreasing settling time for these bits. An error correction stage can then be used to extend settling time permitted at each bit level, and erroneous output digits are corrected digitally. Such a system is presented in U.S. Pat. No. 4,620,179 entitled "Method for Successive Approximation A/D Conversion", to Cooper et al. Cooper et al. state that this approach provides a net savings, because even though the error correction stage adds time to overall conversion, time is saved from the most significant bits.